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WiFi","url":"https://ptob.dev/research/starlink-wifi-timing/"},{"text":"Low-level timing on ESP32-S3","url":"https://ptob.dev/research/esp32-s3-event-capture/"},{"text":"BLE timing tails and multipath","url":"https://ptob.dev/research/ble-timing-tails-multipath/"},{"text":"From BLE to a Pi NTP/PTP gateway","url":"https://ptob.dev/research/pi5-mhat-time-gateway/"},{"text":"From USB frames to a macOS clock","url":"https://ptob.dev/research/usb-macos-time-transfer/"},{"text":"Empirical BLE-trained holdover","url":"https://ptob.dev/research/empirical-ble-holdover/"},{"text":"ESP32-S3 causal clock discipline","url":"https://ptob.dev/research/esp32-s3-causal-clock-discipline/"},{"text":"Timing information and power scheduling","url":"https://ptob.dev/research/awake-timing-power-scheduling/"},{"text":"All research & evidence","url":"https://ptob.dev/research/"}],"text":"# Trustworthy Hardware Timestamps in Zephyr: Event Association, Clock Continuity, and Service Availability\n\nPublic-review research draft  1 November 2026  7 pages · PDF\n\nHow can Zephyr developers turn hardware captures into trustworthy, available time?\n\n[Read PDF](https://ptob.dev/papers/preview/?file=%2Fpapers%2Fzephyr-hardware-timestamps-20261101.pdf)[Cite this edition](https://ptob.dev/research/zephyr-hardware-timestamps/#citation)\n\n## Overview\n\nA precise timer reading can still belong to the wrong packet, a discontinued counter or a stale evaluation instant. This practical study follows PToB’s Zephyr/nRF52840 implementation from radio-event capture through clock publication. It gives developers inspectable contracts, failure cases and an evaluation plan for improving timing while accounting for service availability.\n\n## What this paper covers\n\n- Associate a hardware latch with the correct packet, controller operation and capture epoch; close ownership before reusing resources.\n- Extend a fine counter with continuity checks, use bounded snapshot readers and state the aperture of cross-domain clock reads.\n- Copy source state coherently before reading its evaluation time, preserving original freshness and expiry checks.\n- Evaluate timing error alongside missing observations, false rejection and execution cost instead of reporting only selected residuals.\n\n## Research scope\n\nThe source case study uses pinned Zephyr 4.1.0 dependencies and a single-core nRF52840 configuration. No new comparative hardware experiment or native source-ordering regression run is reported. Historical relative-PPS evidence retains 436 usable observations among 602 opportunities: 65 invalid references, 3 expired maps and 98 unobserved opportunities. It does not qualify current firmware, calibrated UTC or electrical-output accuracy; comparative accuracy, availability and cost measurements remain proposed work.\n\n## Read it in context\n\nUse this paper to review event association, counter lifecycle and source evaluation in your own Zephyr integration. Read the separate ESP32-S3 guide for another implementation and the dated V14 record for the historical measurement population. The author approved this unchanged seven-page draft for public review after its review checkpoint; the PDF retains its earlier author-review and pending-library-inclusion labels. The publication receipt records that later approval. It remains unsubmitted and has not been peer reviewed.\n\n[Paper source and companion records](https://github.com/yantisj2/PToB/tree/main/papers/zephyr-timing)[Public-review approval receipt](https://github.com/yantisj2/PToB/blob/main/papers/zephyr-timing/publication.json)[Read the ESP32-S3 implementation guide](https://ptob.dev/research/esp32-s3-event-capture/)[Inspect the historical one-relay evidence](https://ptob.dev/research/#t096-relay)\n\n## Cite this edition\n\nJonathan Yantis. Trustworthy Hardware Timestamps in Zephyr: Event Association, Clock Continuity, and Service Availability. 1 November 2026. Public-review research draft. [Original PDF](https://ptob.dev/papers/preview/?file=%2Fpapers%2Fzephyr-hardware-timestamps-20261101.pdf).\n\nSummary permalink: [https://ptob.dev/research/zephyr-hardware-timestamps/](https://ptob.dev/research/zephyr-hardware-timestamps/)\n\nJonathan Yantis leads protocol design, hardware development and research. GPT 6.1 contributes implementation, analysis and documentation. This page summarizes the linked edition; retain its original evidence dates and measurement references.\n\n## The full paper\n\nThe original document includes the technical detail and references behind this summary.\n\n[Read PDF](https://ptob.dev/papers/preview/?file=%2Fpapers%2Fzephyr-hardware-timestamps-20261101.pdf)\n[Cite this edition](https://ptob.dev/research/zephyr-hardware-timestamps/#citation)\n\n[Paper sources on GitHub](https://github.com/yantisj2/PToB/blob/main/papers/README.md)\n\n## Continue exploring\n\n[Affordable timing from Starlink over WiFi](https://ptob.dev/research/starlink-wifi-timing/)[Low-level timing on ESP32-S3](https://ptob.dev/research/esp32-s3-event-capture/)[BLE timing tails and multipath](https://ptob.dev/research/ble-timing-tails-multipath/)[From BLE to a Pi NTP/PTP gateway](https://ptob.dev/research/pi5-mhat-time-gateway/)[From USB frames to a macOS clock](https://ptob.dev/research/usb-macos-time-transfer/)[Empirical BLE-trained holdover](https://ptob.dev/research/empirical-ble-holdover/)[ESP32-S3 causal clock discipline](https://ptob.dev/research/esp32-s3-causal-clock-discipline/)[Timing information and power scheduling](https://ptob.dev/research/awake-timing-power-scheduling/)[All research & evidence](https://ptob.dev/research/)"}}