Reducing Timing Tails and Multipath Sensitivity in an Operating BLE Precision Mesh

Overview

This study reviews PToB’s event capture, exact packet association, clock bridging and bounded clock discipline. It separates possible detector bias from packet loss that ages a clock model, then proposes placement, per-channel diagnostics, instrumentation and controlled tests to distinguish the causes of timing tails.

What this paper covers

• Distinguish packet delivery latency, correction age, clock error, availability and recovery.
• Understand why precise event capture does not identify the first RF path or remove clock-offset and delay ambiguity.
• Plan controlled workload and placement comparisons with frozen calibration, complete opportunity counts and held-out validation.

Research scope

No new hardware experiment is reported, and historical timing tails do not identify multipath as their cause. W12, downstream PPS, selected-TX and N30 cohorts retain separate calibration and denominators. First-path detection, calibration portability, absolute UTC and physical output bounds remain unqualified.

Read it in context

Pair this draft with the low-level ESP32-S3 guide to connect capture mechanisms to the remaining diagnostic questions. Read the dated W12 evidence for the existing measured populations. The paper’s experimental matrix and candidate controls are proposed work; they have not been run or qualified by this manuscript.