Low-Level Timing on ESP32-S3: Event Capture, Clock Bridges, and Causal Validation
How can ESP32-S3 event capture support a causally validated software clock?
Overview
This implementation guide follows continuous hardware capture, narrow IRAM clock bridges, exact packet association and causal fitting in W12. Counter arithmetic, pseudocode, offline checks and a practical validation sequence connect low-level events to a published software clock.
What this paper covers
- How clock bridges associate counters without treating packet arrival as a precision reference.
- Why a prediction must be evaluated before its observation is ingested.
- How GNSS witnessing, delivered PPS, estimated TX and internal prediction answer different questions.
Research scope
Counter resolution is not delivered accuracy. The current 24 October W12 record retains 522/600 eligible PPS observations and 78 unavailable records; relay, sampled TX and GNSS-prediction populations stay separate. RF, output timing and calibrated UTC bounds remain unqualified.
Read it in context
Use this guide when implementing or reviewing event capture and clock mapping. The online W12 record supplies the dated measurement populations; the architecture viewer explains the timing path without replacing the implementation references.
Cite this edition
Jonathan Yantis. Low-Level Timing on ESP32-S3: Event Capture, Clock Bridges, and Causal Validation. 24 October 2026. Research draft. Original PDF.
Summary permalink: https://ptob.dev/research/esp32-s3-event-capture/
Jonathan Yantis leads protocol design, hardware development and research. GPT 6.1 contributes implementation, analysis and documentation. This page summarizes the linked edition; retain its original evidence dates and measurement references.